SIG / GND / PWR / SIG
Default for most digital work. Keep L2 continuous under high-speed and RF routes. Treat L3 as a solid as possible power plane and stitch returns with local decoupling when signals change reference.
Most boards that outgrow 2-layer FR-4 need planes, not more copper poured on the outer layers. XFPCB builds 4-layer boards around manufacturable stackups, clear impedance notes, and a DFM pass before CAM release.
Buyers comparing 4-layer PCB options usually want three answers: which stackup is safe for EMI and return current, how impedance is held on a 1.6 mm board, and whether the cost jump from 2-layer is justified. This page focuses on those decisions for factory-direct fabrication at XFPCB.
A 4-layer board adds two inner copper layers that become dedicated ground and power references. That change shrinks loop area, improves power distribution, and makes 50 ohm microstrip or common differential pairs practical without exotic coplanar tricks on a bare 2-layer board.
Default for most digital work. Keep L2 continuous under high-speed and RF routes. Treat L3 as a solid as possible power plane and stitch returns with local decoupling when signals change reference.
Useful when EMI and return integrity matter more than a full power plane. Power can ride as poured shapes on outer layers or as short island pours, with careful via stitching.
1.6 mm remains the common export thickness. Thinner builds (for example 0.8 mm) change via aspect ratio and plane capacitance. Agree pressed dielectric values with CAM before freezing trace widths.
Controlled impedance on 4-layer boards depends on copper weight, soldermask, and the dielectric under the microstrip. Do not rely only on EDA defaults. Put targets in the fab notes (for example 50 ohm single-ended, 90 ohm USB, 100 ohm Ethernet) and allow CAM to adjust widths against the real stackup.
| Factor | What changes at 4 layers |
|---|---|
| Process | Inner-layer etch, oxide, single press cycle, then outer process |
| Materials | Core + prepreg stack instead of a simple double-sided laminate |
| Engineering | Stackup confirmation and optional impedance coupons |
| When it pays off | Fewer EMC respins, cleaner PDN, denser routing without wire jumpers |
If your design still fits 2-layer electrical limits, stay there. If ground stitching and EMI patches keep growing, 4-layer is usually the cheaper path through validation.
Look for unnecessary splits under high-speed routes and for clearance that starves annular rings.
Confirm aspect ratio for finished thickness and copper distribution that limits warp risk.
Match HASL, ENIG, or OSP to assembly needs; keep mask dams realistic for fine pitch.
Verify targets, layer assignment, and whether coupons are required before release.
For general digital and mixed-signal work, SIG / GND / PWR / SIG with a solid L2 ground under the primary routing layer is the usual starting point. Confirm dielectric thicknesses with CAM before locking impedance widths.
Move up when you need a continuous return plane, cleaner EMI behavior, controlled impedance, or when 2-layer jumpers and ground stitching become unreliable.
Yes. State single-ended and differential targets in the fab notes, and we will align stackup and coupon planning during engineering review.
Gerber or ODB++, drill, board outline, preferred stackup or thickness, copper weights, finish, solder mask, quantity, and impedance notes if required.
Share your preferred SIG-GND-PWR-SIG or alternate stack, impedance targets, copper weights, finish, quantity, and schedule. XFPCB CAM will check dielectric fit and producibility.