Lane speed, not the marketing total, sets PCB difficulty for 800G-class AI data-center hardware. An 8x112G PAM4 architecture already squeezes insertion-loss and return-loss budgets; the path toward 224G PAM4 for higher aggregate rates leaves even less room for rough copper, via stubs, and casual connector launches.
Designers who keep routing while stackup and back-drill maps stay "TBD" discover the gap when VNA coupons fail after mechanical outlines freeze. Materials, HVLP-class foils on critical layers, stub control, and launch geometry need to be RFQ inputs, not afterthoughts.
From aggregate bandwidth to channel physics
400G, 800G, and next-rate systems describe total throughput. PCB risk tracks baud rate and Nyquist content. PAM4 improves spectral efficiency but reduces voltage margin, so the same via stub or impedance bump that was tolerable at lower rates becomes a yield and BER problem.
Channel elements include package breakout, PCB traces, vias, connector launches, and module interfaces. Model the path as one system. Optimizing only trace width while ignoring anti-pads and back-drill depth is incomplete SI work.
Insertion loss, return loss, crosstalk, skew
Insertion loss accumulates dielectric loss, conductor loss, via loss, and connector loss. Long routes on mid-loss materials with rough foil burn budget before the connector. Return loss tracks discontinuities at breakouts, vias, and launches. Crosstalk rises with dense lane packing and broken references. Skew from length mismatch or glass-weave effects eats eye margin at these rates.
Practical responses: shorten critical channels, reduce unnecessary layer hops, specify smoother copper on SerDes layers, use spread-glass constructions where weave skew matters, and keep differential geometry consistent.
Materials and copper on purpose
Ultra-low-loss laminates on every layer are rarely required. Hybrid stackups place premium Df performance on loss-critical strata and more economical materials elsewhere. Evaluate Df, Dk stability, Tg/CTE, moisture, and weave - not brand slogans alone.
Copper roughness is part of the SI model under skin effect. Call out foil requirements on critical layers early so lamination recipes and availability are confirmed before layout lock.
Vias, back-drill, and HDI breakout
Unused via stubs resonate and reflect. Back-drill notes should list nets, sides, target layers, and maximum residual stub. Dense switch ASICs, DSPs, and optical interfaces often need HDI microvias or via-in-pad to escape without marathon through-hole stubs.
Connector launches deserve the same rigor as mid-board traces: pad/anti-pad geometry, via pattern, and reference continuity belong in the design review, not only in a field-solver screenshot nobody sent to CAM.
Stackup and DFM alignment
Freeze dielectric heights, copper weights, impedance targets, and reference plan before detailed routing. Crossing splits or orphaning returns undoes careful width calculators. Ask for TDR/VNA coupon correlation on the production stackup.
Before release, confirm material availability, foil class, back-drill capability, HDI sequence, and test coupon scope with the fabricator. Building today's 800G channel with measurable loss and stub data is also how teams prepare for tighter next-rate budgets.
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