Standard SMT mounts packaged components onto a PCB. Advanced SMT packaging is what happens when the product needs chip-level density: bare die on board, flip-chip bumps, multi-chip modules, and vertical stacking. The shared goal is shorter interconnects, higher I/O in less area, and system functions that no longer fit in a flat sea of SOP parts.
Overseas teams evaluating China PCBA partners should read "advanced packaging" as a process-capability claim. Ask which technologies are actually in production, which are engineering samples, and what inspection and underfill controls come with them.
From DIP to area-array, then to bare die
Packaging history moved from through-hole DIP to SOP and QFP, then to BGA and CSP as pin counts rose and outlines shrank. Bare-die assembly grew as low-CTE materials, bumping, and underfill chemistry became production-worthy for products such as dense compute, storage, and portable electronics.
Two foundational bare-die approaches dominate board-level discussion: chip-on-board (COB) and flip chip.
COB: wire-bonded die on the PCB
COB attaches a bare die to the board with adhesive, bonds aluminum or gold wires from die pads to PCB pads, then protects the die and wires with epoxy. Pads are typically around the die perimeter. The method saves package overhead and can be cost-effective for low-power ICs, often in the sub-watt class depending on thermal design.
Limits are real. COB is less natural for high-volume pick-and-place rhythms than taped SMD parts, PCB quality must support fine bond pads, and heat removal is constrained compared with many bumped solutions. It is a mature tool for the right power and volume profile, not a universal miniaturization hammer.
Flip chip: bumps and face-down attach
Flip chip forms solder bumps on die I/O, flips the die face-down, aligns bumps to pads, and reflows. Area-array I/O replaces peripheral wire bonds, shortening paths and raising interconnect density. Process control around bump quality, pad design, alignment, underfill, and warpage becomes the yield story.
IBM's historical C4 (controlled collapse chip connection) work highlighted why the method can be robust: molten solder surface tension aids self-alignment, and collapse under gravity is controlled rather than chaotic. Modern products inherit those physics even when the materials stack has evolved.
MCM: several chips, one module
A multi-chip module integrates multiple ICs on a shared substrate so the module behaves like a small subsystem. Typical traits include multilayer wiring, high I/O counts, and the ability to mix CSP, flip chip, and ASIC devices. Variants are often grouped as:
- MCM-L: high-density interconnect on laminate/PCB-like technology
- MCM-C: ceramic multilayer with thick- or thin-film processes for demanding reliability
- MCM-D: deposited thin-film multilayer on silicon or advanced substrates, usually the most process-intensive
MCM shows up where speed, density, or system partitioning justifies module-level integration before the cards hit a standard motherboard.
3D assembly: using the Z-axis
Three-dimensional assembly stacks dice, MCM layers, or wafer-scale devices and connects them vertically. Embedded structures bury passives or ICs inside multilayer media with SMDs on top. Active-substrate approaches build interconnect on a silicon WSI base. Stacked MCM structures interconnect upper and lower modules.
Benefits can include higher density, shorter vertical paths, and more function per volume. Complexity, test access, thermal stacking, and known-good-die strategy rise with the ambition.
What this means for board and assembly planning
COB, flip chip, MCM, and 3D packaging are stages on the same density curve, not competing slogans. For a conventional SMT house, the near-term "advanced" reality is more often fine-pitch BGA, 0.4 mm QFN, PoP, and dense passive clusters that already stress stencil, placement, reflow, and inspection as one window.
If your NPI includes true bare-die or module work, bring process notes early. For fine-pitch packaged work that still lives in mainstream SMT, lock paste strategy for bottom-termination centers, void criteria, and whether SPI/X-ray are mandatory. XFPCB SMT PCB assembly planning should include PCB SMT stencil design (and step stencil where copper geometry demands it) before anyone blames the placer for a window that was never defined.