Overseas buyers often jump from a two-layer prototype to a four-layer production board for one reason that has nothing to do with fashion: return current needs a nearby plane. Dense MCU escape, USB or Ethernet pairs, mixed analog sensing, and tighter EMI margins all push layouts past what top-and-bottom copper can cleanly support.
A four-layer board is still the workhorse multilayer for industrial controllers, IoT modules, automotive interfaces, and compact consumer products. Cost stays far below six- or eight-layer builds, while the internal planes give you routing room and a stable reference that two-layer boards struggle to match.
What a 4-layer board actually buys you
Four copper layers separated by dielectric are not "two extra layers of wire." The usual arrangement puts components and signals on the outer layers and reserves the inner layers for ground and power (or a second ground). Signals that sit close to a continuous reference plane have shorter, more predictable return paths. That predictability shows up as cleaner edges, fewer EMI surprises, and more repeatable impedance on moderate-speed links.
Compared with two-layer construction, four layers typically improve routing organization, plane continuity, mixed-signal partitioning, and EMI control. Two-layer remains fine for simple, low-density boards. Four layers become the better commercial choice when density, grounding quality, or signal behavior starts to dominate the schedule risk.
Stackup choices that matter in quoting
Stackup is the layer order plus dielectric spacing. It drives signal integrity, crosstalk, EMI, impedance, and how a China fab will actually press the panel.
A common baseline is:
- Layer 1: Signal
- Layer 2: Ground
- Layer 3: Power
- Layer 4: Signal
That Signal-Ground-Power-Signal menu works well for many general digital and mixed-signal products. When both outer layers carry timing-critical pairs, a Signal-Ground-Ground-Signal construction can give each outer layer a solid reference, provided power distribution still has enough pour and decoupling discipline.
Do not pick a stackup by habit. Match it to electrical goals:
- General digital: S-G-P-S is usually enough.
- Higher-speed outer routing: prioritize continuous references on both outer layers.
- Mixed-signal: plan return continuity and domain separation as carefully as copper area.
- Power-heavy control boards: improve PDN without starving signal references.
Finished thickness options such as 0.8 mm, 1.0 mm, 1.2 mm, 1.6 mm, and 2.0 mm are all common. 1.6 mm remains the default for many connectors and card guides. Thinner builds change dielectric spacing and impedance, so re-check controlled traces before release.
Impedance without guessing the fab menu
Controlled impedance on four layers is a stackup problem first and a trace-width problem second. Dielectric thickness, Dk, copper weight, geometry, and distance to the reference plane all move the ohms result. A 50-ohm line on one fabricator's standard 4-layer menu can need a different width on another menu with the same layer count.
Best practice for overseas RFQs: freeze the intended construction with the manufacturer before locking impedance-critical routing. Include ohms target, reference layer, tolerance, copper weight, and whether coupons are required. If the board is low-speed only, waive impedance explicitly so quotes stay comparable.
Layout habits that keep EMI and yield under control
Keep high-speed routes adjacent to solid reference planes. Avoid routing across plane splits; the return current detour is a classic EMI and SI failure. Route clocks, differentials, and sensitive analog nets before general wiring consumes the board. Control spacing on aggressive nets, use vias intentionally rather than casually, and plan power and decoupling early instead of treating them as leftover pours.
Copper balance also matters. Heavy copper on one layer with thin cores elsewhere can produce warp that fine-pitch placement cannot fully correct. If you need 2 oz on power while keeping controlled impedance on signals, say so early so dielectrics and line widths are co-designed.
Manufacturing notes CAM actually uses
Four-layer fabrication is mainstream: inner-layer pattern and etch, lamination, drill and plate, outer pattern and etch, mask and finish, then electrical test. Even so, stackup choices still affect yield, impedance consistency, and cost.
Before you release Gerbers, confirm finished thickness and tolerance, copper weights, impedance requirements or an explicit waiver, material system, and whether you need a standard or custom menu. Attach the same revision of stackup notes that matches the files you want priced. For 4 layer PCB builds with controlled traces, also include an impedance control PCB note set and the usual manufacturing files package.
If assembly is in scope, send BOM, CPL, and assembly drawing with the fab package so fiducials, polarity, and paste rules are reviewed in one pass. That single revision package is often what separates a smooth NPI from a week of email about mismatched stackup assumptions.